CMOS logic family | NMOS and PMOS
CMOS logic family is a group of logic circuits, built with complementary MOS devices. All the logic gates that are built with MOSFET devices will come under MOS logic family. MOS Logic family can be classified into three categories. They are
- NMOS logic family – built with N-channel Metal oxide semiconductor FET (MOSFET)
- PMOS logic family – built with P-channel Metal oxide semiconductor FET (MOSFET)
- CMOS logic family – built with both N-channel and P-channel Metal oxide semiconductor FET (MOSFET)
Off all the MOS families, NMOS and CMOS are used in making an integrated circuit. It is because of its advantages.
NMOS Logic circuits
In the N-channel MOS family, current conduction is because of the electrons. The negatively charged electrons are fast-moving than holes, which is positively charged. So the speed of operation of NMOS is faster than PMOS.
Let us discuss the family of NMOS logic devices in detail.
The NMOS inverter circuit has two N-channel MOSFET devices. Among the two MOSFETs, Q1 acts as the load MOSFET, and Q2 acts as a switching MOSFET.
Since the gate is always connected to the supply +VDD, the MOSFET Q1 is always ON. So, the internal resistance of Q1 acts as the load resistance RL. Compared to both MOSFETs, Q1 is designed to have more resistance than Q2.
When zer0 voltage(LOW input) is given at the gate terminal of Q2, it is turned OFF. It will make the output V0 to be HIGH, which is the supply voltage.
When HIGH input is given at the gate terminal, the MOSFET Q2 will be turned ON, which will make the output VO be at LOW value.
NMOS NAND gate
The figure shown below is the circuit of the 2-input NMOS NAND gate. It consists of three N-channel MOSFETs, in which Q1 acts as the load resistance, whereas Q2 and Q3 act as the switching MOSFETs. The two inputs A and B are given to MOSFET Q2 and Q3 respectively.
When both inputs A and B are given LOW input, both the MOSFETs are turned OFF, which makes the output V0 as HIGH.
When either A or B is LOW, the MOSFET with low input will be turned OFF, thus making the output to be HIGH.
If HIGH input is given to both the input terminals, it will turn ON the MOSFETs Q2 and Q3. Therefore, the current due to the supply voltage VDD will flow towards the ground making the output as LOW.
NMOS NOR gate
The following circuit shows the circuit of the 2-input NMOS NOR gate. It has 3 N-channel MOSFETs, in which Q1 acts as the load resistance, MOSFETs Q2 and Q3 act as switching devices.
If Low input is given at both the inputs, it will turn OFF both the MOSFETs Q2 and Q3, thereby making the output to be HIGH.
If any of the input, either A or B is given HIGH input, the corresponding MOSFET with HIGH input will turn ON making the output to be LOW. Similarly, if both the inputs are HIGH, it will turn ON both the MOSFETs, which will make the output to be LOW.
PMOS Logic Circuits
As discussed above, the digital logic family can be built with P-channel MOSFETs and those circuits are known as PMOS logic circuits. The operation of PMOS is similar to the NMOS circuits, except that the mode of conduction is different.
For a P-channel MOSFET, a negative voltage is to be given at the gate terminal to create a channel. Thus negative voltage(LOW voltage) is enough to turn ON the PMOS devices.
CMOS Logic Circuit Family
CMOS(Complementary MOS) logic family uses both N-channel and P-channel MOSFET devices. CMOS has greater complexity than PMOS and NMOS. However, the speed of operation is high and power dissipation is less in CMOS. CMOS also has more fan-out and better noise margin.
Now let us look at the CMOS logic family.
In CMOS inverter, both the n-channel and p-channel devices are connected in series. The source terminal of the P-channel device is connected to source voltage +VDD.
The source terminal of the N-channel device is connected to the ground. The gate of both the devices are connected together and a common input is given to both the MOSFET device. The drain terminals are connected together as a common output.
For a HIGH input at VIN, the P-channel MOSFET(Q1) gets turned OFF, but the N-channel device(Q2) will be turned ON. This will drive the output Vo to be at Logic LOW.
If LOW input is given at the input terminal VIN, it will turn ON on Q1 and turn OFF Q2, making the output to be HIGH.
CMOS NAND gate
The circuit shown below shows the circuit of the 2-input CMOS NAND gate. It has two p-channel MOSFETs (Q1, Q2) and two n-channel MOSFETs (Q3 and Q4).
A and B are two inputs. The input A is given to the gate terminal of Q1 and Q3. The input B is given to the gate terminal of Q2 and Q4. The output is obtained from the terminal VO.
When both the inputs are given LOW input, it will turn ON Q1, Q2 and turn OFF the MOSFETs Q3 and Q4. The output terminal is connected to the supply voltage VDD and the output will be HIGH. It is shown in the below diagram(a).
When either one of the input is high, for eg., Let us consider A is given HIGH input and B is given LOW input. In this case, MOSFETs Q1 and Q4 get turned ON, whereas Q2 and Q3 are turned OFF as shown in the diagram(b) below. This will make a path for the supply voltage to be connected to the load, making the output to be HIGH.
If both the inputs A and B are HIGH inputs, which make the MOSFETs Q3, Q4 to be turned ON and Q1, Q2 to be turned OFF. Thus the output is connected to the ground alone as shown below(c). Thereby, the output will be at LOW value.
CMOS NOR gate
Similar to other logic family, CMOS NOR gate circuit also has two NMOS and two PMOS devices and the input and output are connected as shown in the below figure.
The operation of 2-input CMOS NOR gate is shown in the below figure.
For the LOW inputs at A and B, PMOS devices Q1 and Q2 will conduct, making the output to be at logic HIGH. When any one of the input is LOW, it will produce a LOW output as shown in the below figure(b).
If both A and B are given HIGH input, it will turn ON the PMOS devices Q3 and Q4, making the output voltage to be logic LOW. It is shown in figure(c).
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