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Asynchronous counter / Ripple counter – Circuit and timing diagram

by | Last updated Nov 13, 2020 | Sequential Circuits

The asynchronous counter is a sequential circuit used to count the clock pulses. It has a series of flip-flops connected together. The clock pulse is given to the first flip-flop. The output of each flip-flop is fed as the clock input for the higher-order flip-flop. The asynchronous counter is also called a ripple counter.

For the design of the asynchronous counter, T flip-flops are used. Because the output toggles in T flip-flop. In other words, this flip-flop produces complementing output. That is, if 0 is given as the input, 1 is produced at the output and vice versa.

The flip-flop used for the asynchronous counter is negative edge-triggered flip-flops. It means, the flip-flop will change its state at the falling edge of the clock pulse.

In this article, we will discuss the asynchronous up counter, asynchronous down counter and asynchronous up/down counter.

2-bit asynchronous up counter

For a 2-bit asynchronous counter, 2 flip-flops are used as shown in the below figure. It is an up counter, where the count is incremented for each clock pulse. A 2-bit counter will have 22 = 4 distinct states(00, 01, 10, 11).

2-bit asynchronous up counter

The clock pulse input is given to the first flip-flop only. The output(QA) of the first flip-flop is fed as the clock input for the second flip-flop. The HIGH or logic 1 is maintained at the T-input of both flip-flops.

The clock pulse is digitally counted at the output QA and QB, where QA is the Least significant bit(LSB) and QB is the most significant bit(MSB).

Operation

Let us assume the initial state of flip-flop as QBQA = 00. During the first clock pulse, that is at the falling edge of the clock pulse, JK FF1 will toggle its output state to logic 1. For the next clock pulse, again JK FF1 will toggle its output to logic 0. The toggling of JK FF1 continues for each clock pulse.

Now, What about the state of JK FF2 ?

The output of the first flip-flop(JK FF1) is given as a clock pulse input for the second flip-flop(JK FF2). Whenever the QA output goes high, at the falling edge of its output, the JK FF2 will get triggered. When the JK FF2 gets triggered, it produces a toggled output.

As we have assumed the initial state of JK FF2 as QB = 0, the output will get toggled to QB = 1. This output again toggles, when the output of JK FF1 goes high HIGH.

The change of state of flip-flops for each occurrence of the clock pulse is shown in the below timing diagram. As you can observe from the timing diagram, the counter counts from o0 to 11. After reaching 11, the counter resets to 00 and starts to count from 00 again.

timing diagram of 2-bit asynchronous up counter

3-bit asynchronous up counter

The 3-bit asynchronous or ripple up counter is similar to the 2-bit ripple up counter. Here for a 3-bit counter, an additional flip-flop is added. Thus for the 3-bit asynchronous counter, 3 T-flip-flops are used.

This counter consists of 23 = 8 count states(000, 001, 010, 011, 100, 101, 110, 111). The counter counts the incoming pulses starting from 0 to 7.

3-bit asynchronous up counter

The above circuit shows the circuit diagram of a 3-bit asynchronous up counter, in which the clock pulse is given as clock input for JK FF1. For the other flip-flops, the clock input is fed from the output of previous flip-flops.

The clock pulse count is noted at the output of each flip-flop(QCQBQA), where QA is the LSB and QC is the MSB.

The operation is the same as the 2-bit asynchronous up counter. At the falling edge of each clock pulse, the output of JF FF1 toggles. For each logic HIGH output(QA = 1) of JK FF1, at its falling edge, JK FF2 will toggle the output(QB). Similarly, for each logic HIGH output(QB = 1) of JK FF2, JK FF3 will toggle the output(QC).

The below figure shows the timing diagram of the 3-bit ripple counter, which shows the change of state of each flip-flop during each clock pulse. In this type, the counter resets to 000, after counting up to 111.

timing diagram of 3-bit asynchronous up counter

3-bit asynchronous down counter

The down counter will count the clock pulses from maximum value to zero. In other words, for each clock pulse, the count value is decremented.

The below diagram shows the 3-bit asynchronous down counter. Since it is a 3-bit counter, 3 negative edge-triggered flip-flops are used. The clock pulse input is given only to the first flip-flop. The clock input of the remaining flip-flops is triggered by the Q output of the previous flip-flop.

Since it is down counter, the 3-bit count value is measured from the (\overline{Q}_{C} \overline{Q}_{B} \overline{Q}_{A}), where \overline{Q}_{C} is the MSB and \overline{Q}_{A} is the LSB.

3-bit asynchronous down counter

The operation is the same as that of the 3-bit asynchronous up counter. If the output is taken at the normal Q output of each flip flop, then it is an up counter. If the output is taken at the complemented output (\overline{Q}) of each flip flop, it is said to be the down counter.

The change of state of each flip flop with respect to the clock pulse and the count value is shown in the below timing diagram.

In this diagram, the output waveform QC, QB, QA represents the normal Q output of JK FF3, JK FF2 and JK FF1 respectively. The output waveform \overline{Q}_{C}, \overline{Q}_{B}, \overline{Q}_{A} represents the complemented output from of JK FF3, JK FF2 and JK FF1 respectively.

The count value can be observed from the complemented outputs. The counter value starts from 111 and decrements its value for each clock pulse. After reaching 000, the counter resets to the maximum value(111) and starts to decrement again for the next clock pulse.

Asynchronous Up/Down counter (or) Bidirectional counter

For asynchronous up/down counter, control input is necessary for the control of the operation as up or down counter.

When the control input is 0, in the following figure, the AND gates 1 and 3 are disabled. It enables gate 2 and 4, which means, \overline{Q} output of first and second flip-flop drives the clock input of JK FF2 and JK FF3 respectively. In this case, the counter will perform the operation of the down counter.

Asynchronous Up/Down counter

When the control input is 1, gates 1 and 3 are enabled and gates 2 and 4 are disabled. This makes a way for the Q output of flip-flops to drive the clock input of the next stage flip-flop. Now, the counter will perform the up counter operation.

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