SR flip flop is the basic building block of D flip flop. As we know, SR flip flop has two inputs (S, R) and two outputs(Q and Q’).
When you look at the truth table of SR flip flop, you can observe the following. The S input is made high to store logic 1 or to SET the flip flop. Similarly R input is made high to store logic 0 or to RESET the flip flop. When both the inputs are the same, the output either does not change or it is invalid.
The states obtained for the same input are not necessary for most of the applications. Such applications require only SET and RESET states. For those applications, we can use the S and R inputs which are always complement to each other. The flip flop with such functionality is called as Data flip-flop or Delay flip-flop or D flip-flop.
Circuit of D flip-flop
D Flip Flop is the most important of all the clocked flip-flops as it ensures that both the inputs S and R are never the same at the same time. It is constructed by joining the S and R inputs with an inverter in between them, as shown below. Thus the D flip flop has single input(D).
As you can observe from the circuit above, the input D is applied to the input of SR flip flop. The ‘Set’ input of the SR flip flop receives the D input and the ‘Reset’ input receives the complement of D input(D’).
Now, lets take a look at how the D flip flop operates.
Operation and truth table of D flip-flop
If D = 1, then the inputs for the SR flip flop are S = 1, R =0. When you look at the truth table of SR flip flop, the next state output is logic 1, which will SET the flip flop.
When D = 0, the inputs of SR flip flop will become, S = 0, R = 1. This input combination for the SR flip lop will produce logic LOW value, which will RESET the flip flop. The truth table of the D flip-flop is shown below.
In simple words, we can say that, when the clock pulse is given, the output Q follows the D input of the flip flop.