Transistor-Transistor Logic belongs to the digital logic family. It consists of transistors at both input and output side, diodes and few resistors.
The TTL integrated circuits are very popular in different applications including computer controls, consumer electronics, industrial control systems, etc.
There are various subfamilies in transistor-transistor logic, which includes standard TTL, Low power TTL, Schottky TTL, Advanced Schottky TTL, High power TTL, fast TTL, etc. In this section, you will learn about the circuit and operation of standard TTL and different output configurations of TTL.
Circuit of standard 2-input TTL NAND Gate
The following figure shows the circuit diagram of the 2-input TTL NAND gate. It has four transistors Q1, Q2, Q3 and Q4. Transistor Q1 has 2-inputs on the emitter side. Transistor Q3 and Q4 form the output side, called Totem pole output.
The circuit of a 2-input TTL NAND gate may look complex. We can simplify its operation by considering the diode equivalent of the 2-input NPN transistor, as shown in the below figure.
In the figure, diodes, DA and DB represent the 2-input emitter junction of transistor Q1. Diode DC represents the collector-base junction of transistor Q2.
Operation of 2-input TTL NAND Gate
When both inputs A and B are low, both the diodes are forward biased. So the current due to the supply voltage +VCC = 5 V will go to the ground through R1 and the two diodes DA and DB.
The supply voltage gets dropped in the resistor R1 and it will not be sufficient to turn ON the transistor Q2. With Q2 open, the transistor Q4 will also cut off. But the transistor Q3 is pulled high. Since Q3 is an emitter follower, the output at the terminal will also be HIGH, which is at logic 1.
When any one input, either A or B is low, the diode with low input will be forward biased. The same operation will take place as explained above. In this case, the output will be HIGH.
When both the inputs A and B are high, both the diodes at the emitter-base junction will be reverse biased. The diode DC at the collector-base junction is forward biased. It will turn on the transistor Q2. With Q2 turned ON, transistor Q4 will also be turned ON.
Both the transistors at the output side will conduct and so the output at terminal will have LOW value, which is considered as logic 0.
Circuit of standard 3-input TTL NAND Gate
The following figure shows the circuit of the standard 3-input TTL NAND gate. It is the same as that we discussed in the 2-input TTL NAND gate circuit, except that here, the input transistor Q1 has three emitters instead of two. The operation is the same as the 2-input TTL NAND gate.
Output configuration of TTL
There are three different output configurations in transistor-transistor logic
- Totem-pole output
- open collector output
- Tri-state gate output
In the circuit shown below, the shaded portion shows the totem-pole output. Transistor Q3, Q4, diode D and current limiting resistor R3 form the totem-pole output configuration of TTL.
There are a few advantages of using this configuration. When the output switches from LOW to a HIGH state, the output transistor Q4 goes from saturation to cut off. During this transition, the load capacitance across Q3 charges exponentially from low to a high voltage level.
Due to the low output impedance of both transistors Q3 and Q4, the output voltage can change quickly from LOW to HIGH value as the capacitance charge and discharge quickly.
Open collector output
The open-collector output configuration of Transistor-Transistor Logic is shown in the below figure. In this configuration, the transistor Q3 and pull-up resistor is eliminated. Instead, external pull up resistor for proper operation as shown in the figure.
The output is taken from the open collector terminal of Q4. When transistor Q4 is OFF, the output Y will be HIGH and when Q4 is ON, the output will be LOW.
Tri-state gate output
While operating the transistor in this output configuration, it is possible to attain high speed. Three output state is possible: HIGH, LOW and high impedance.
When the transistor Q3 is ON, the output at terminal Y is HIGH. The output is LOW when the transistor Q4 is turned ON. The first and second states are the normal operation of TTL. In the third state, both the transistors Q3 and Q4 are turned OFF, which results in neither LOW nor HIGH output.