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# Programmable Logic Array (PLA)

by | Last updated Dec 15, 2020 | Programmable Logic Devices

Programmable Logic Array is a type of PLD, which has both programmable AND array and programmable OR array.

In a combinational circuit, because of don’t care conditions, not all the minterms are used. In the case of PROM, where the AND matrix is fixed, all the product terms are not used. This makes the PROM PLD to poor utilization.

If the number of don’t care conditions is more, then PROM will be not suitable for efficient usage. Hence, it is very necessary to switch to a more economical device, called Programmable Logic Array(PLA).

PLA is somewhat similar to the PROM. Both have a programmable OR array, but in PLA, there is a modification in the AND array. PLA does not generate all the minterms, rather depending on the function, the required product terms can be obtained.

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## Block Diagram of Programmable Logic Array

The following figure shows the block diagram of programmable logic array.

It consists of n-inputs, inverters, input buffer, m-outputs and an output buffer. Both AND and OR array have fuses at the inputs, which makes them to be programmable.

The AND matrix or array produces product terms, through the AND gates, which are ORed to get the required function.

In PLA, the input buffers are used to limit the loading of the sources that drive the inputs. The driving capacity of PLA device is increased with the help of output buffers.

An example of PLA circuit of a combinational circuit is shown below. As you can observe from the circuit diagram, it is similar to the PROM circuit, except that the AND array consists of fuses, to program according to the user requirements.

The sequential circuits can also be implemented with PLA. For such implementation, flip-flops are also provided at each output of the OR matrix.

Now let us look at some examples of realization of combinational circuit using PLA.

## Solved example 1

In this example, let’s see how to realize the Boolean expression X = AB + AB’C’ + BC’ and Y = BC + A’BC’ + ABC using Programmable Logic Array.

For the given problem, there are three inputs(A, B, C) and two outputs(X, Y). The complement of three inputs are obtained through NOT gates. Thus the realization has six input lines(input with its complement).

The given expression has six product terms and so the fuses are placed in the corresponding literals to obtain the product terms.

Two OR gate arrays are used at the output to realize the the two functions. The fuses are placed at the corresponding product terms for each Boolean function.

## Solved example 2

For this example, let us realize a boolean functions F1(A, B, C) = ∑ m(1, 3, 6, 7) and F2(A, B, C) = ∑ m(0, 2, 4, 5) using PLA.

Here, two boolean functions are given in terms of minterms. To obtain the expression, the given function is implemented using Karnaugh map.

Thus for the two obtained expressions, the PLA circuit is realized. For which, there are three inputs(A, B, C) and two outputs(F1, F2). In the obtained expressions, there are four product terms and so four AND gate array is used. Two OR gates are used to generate the two boolean fuctions.

The realization of the given Boolean function is drawn below.